1. Field of the Invention
The present invention relates to a lightly doped drain (LDD)-structured and buried channel-type field-effect semiconductor device having, what is referred to as "a pocket layer". The invention also relates to a method of manufacturing the semiconductor device.
2. Description of the Related Art
FIG. 3 illustrates an example of a conventional p-channel transistor of the above type. In this transistor, a p.sup.-- -type diffusion layer 12 for making adjustments to the threshold voltage is deposited in the vicinity of the surface of an n.sup.- -type Si substrate 11. A SiO.sub.2 film 13, serving as a gate oxide film, is further formed on the surface of the Si substrate 11.
An n-type impurity-doped polycrystal Si film 14 and a WSi.sub.x film are stacked on the SiO.sub.2 film 13 and patterned so as to form a gate electrode 16. An impurity is ion-implanted through a mask formed of the gate electrode 16 so as to form p.sup.- -type diffusion layers 17. An impurity is further implanted through the gate electrode 16 and the like used as a mask according to an obliquely rotational ion implantation method so as to form n-type diffusion layers 21 which are referred to as "pocket layers".
A spacer 23 formed of a SiO.sub.2 film 22 is formed on the lateral surface of the gate electrode 16. P.sup.+ -type diffusion layers 24 are formed by impurity ion implantation through a mask formed of the gate electrode 16 and the spacer 23. When the transistor is in the conducting state without the application of an energizing voltage to the transistor's drain, a depletion layer 25 is formed in a region surrounded by the dotted line shown in FIG. 3, the diffusion layers 17 and 24 and the SiO.sub.2 film 13.
Variations in the thickness of the SiO.sub.2 film 22 deposited according to the CVD process and variations in the amount of etch back with respect to the SiO.sub.2 film 22 further cause variations in the width of the spacer 23. In particular, as illustrated in FIG. 4, the SiO.sub.2 film 22 is deposited according to the CVD process so that the thickness d.sub.1 of a region of the film in which the gate electrodes 16 are sparsely disposed is larger than the thickness d.sub.2 of a region of the film in which the gate electrodes 16 are densely arranged. Accordingly, variations in the width of the spacer 23 are affected mostly by the dependency of the thickness of the SiO.sub.2 film 22 on the density of the gate electrodes 16.
On the other hand, the diffusion layers 24 are produced by ion implantation through a mask formed of the gate electrode 16, the spacer 23, and so on, as described above. Accordingly, variations in the width of the spacer 23 further bring about variations in the position of the diffusion layers 24 in the longitudinal direction of the channel. Also, if the gate length of a buried channel transistor is not longer than approximately 0.4 .mu.m, the diffusion layers 21 serving as pocket layers are essential in order to inhibit the short channel effect.
As is clearly seen from FIG. 3, however, variations in the position of the diffusion layers 24 in the longitudinal direction of the channel change the positional relationship between the diffusion layers 21 and the depletion layer 25, which further varies the amount of impurities contained in the diffusion layers 21 within the depletion layer 25. This varies the threshold voltage of the transistor, thereby causing a yield reduction of transistors, as well as increasing the current during standby.